/**HEADER********************************************************************
* 
* Copyright (c) 2008 Freescale Semiconductor;
* All Rights Reserved
*
*************************************************************************** 
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR 
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  
* IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
* THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************
*
* $FileName: lwgpio_mpc8308.h$
* $Version : 3.8.3.1$
* $Date    : Feb-13-2012$
*
* Comments:
*
*   The file contains definitions used in user program and/or in other
*   kernel modules to access GPIO pins
*
*END************************************************************************/
#ifndef __lwgpio_mpc8308_h__
#define __lwgpio_mpc8308_h__ 1

#define LWGPIO_PIN_VALID (0x80000000) /* Note: this is for backwards compatibility with GPIO driver only */

/* Pin field definitions */
#define LWGPIO_PIN_SHIFT (0)
#define LWGPIO_PIN_MASK (0x1F << LWGPIO_PIN_SHIFT)

#define LWGPIO_PIN_FROM_ID(id) (((id) & LWGPIO_PIN_MASK) >> LWGPIO_PIN_SHIFT)

#define LWGPIO_PIN(x) (((x) << LWGPIO_PIN_SHIFT) & LWGPIO_PIN_MASK)

/* Port field definitions */
#define LWGPIO_PORT_SHIFT (9)
#define LWGPIO_PORT_MASK (0x3 << LWGPIO_PORT_SHIFT)
#define LWGPIO_PORT(x) (((x) << LWGPIO_PORT_SHIFT) & LWGPIO_PORT_MASK)
#define LWGPIO_PORT_A   (LWGPIO_PORT(1) | LWGPIO_PIN_VALID)
#define LWGPIO_PORT_B   (LWGPIO_PORT(2) | LWGPIO_PIN_VALID)
#define LWGPIO_ESDHCA   (LWGPIO_PORT(3) | LWGPIO_PIN_VALID)
#define LWGPIO_ESDHCB   (LWGPIO_PORT(4) | LWGPIO_PIN_VALID)
#define LWGPIO_ESDHCC   (LWGPIO_PORT(5) | LWGPIO_PIN_VALID)
#define LWGPIO_IEEEA    (LWGPIO_PORT(6) | LWGPIO_PIN_VALID)
#define LWGPIO_GTM      (LWGPIO_PORT(7) | LWGPIO_PIN_VALID)
#define LWGPIO_IEEEB    (LWGPIO_PORT(8) | LWGPIO_PIN_VALID)
#define LWGPIO_ETSEC2   (LWGPIO_PORT(9) | LWGPIO_PIN_VALID)

#define LWGPIO_PIN0   (0)
#define LWGPIO_PIN1   (1)
#define LWGPIO_PIN2   (2)
#define LWGPIO_PIN3   (3)
#define LWGPIO_PIN4   (4)
#define LWGPIO_PIN5   (5)
#define LWGPIO_PIN6   (6)
#define LWGPIO_PIN7   (7)
#define LWGPIO_PIN8   (8)
#define LWGPIO_PIN9   (9)
#define LWGPIO_PIN10  (10)
#define LWGPIO_PIN11  (11)
#define LWGPIO_PIN12  (12)
#define LWGPIO_PIN13  (13)
#define LWGPIO_PIN14  (14)
#define LWGPIO_PIN15  (15)
#define LWGPIO_PIN16  (16)
#define LWGPIO_PIN17  (17)
#define LWGPIO_PIN18  (18)
#define LWGPIO_PIN19  (19)
#define LWGPIO_PIN20  (20)
#define LWGPIO_PIN21  (21)
#define LWGPIO_PIN22  (22)
#define LWGPIO_PIN23  (23)

typedef struct {
    uint_32 pinmask; /* since struct holds one pin, pinmask will have only one bit set */
    uint_32 flags;
    uint_32 port_idx;
} LWGPIO_STRUCT, _PTR_ LWGPIO_STRUCT_PTR;

#define LWGPIO_MUX_A0_GPIO  (0)
#define LWGPIO_MUX_A1_GPIO  (0)
#define LWGPIO_MUX_A2_GPIO  (0)
#define LWGPIO_MUX_A3_GPIO  (0)
#define LWGPIO_MUX_A4_GPIO  (0)
#define LWGPIO_MUX_A5_GPIO  (0)
#define LWGPIO_MUX_A6_GPIO  (0)
#define LWGPIO_MUX_A7_GPIO  (0)
#define LWGPIO_MUX_A8_GPIO  (0)
#define LWGPIO_MUX_A9_GPIO  (0)
#define LWGPIO_MUX_A11_GPIO (0)
#define LWGPIO_MUX_A12_GPIO (0)
#define LWGPIO_MUX_A13_GPIO (0)
#define LWGPIO_MUX_A14_GPIO (0)
#define LWGPIO_MUX_A15_GPIO (0)
#define LWGPIO_MUX_A16_GPIO (0)
                             
#define LWGPIO_MUX_B10_GPIO (0)

#define LWGPIO_MUX_SDHCA16_GPIO (3)
#define LWGPIO_MUX_SDHCA17_GPIO (3)
#define LWGPIO_MUX_SDHCA18_GPIO (3)
#define LWGPIO_MUX_SDHCA19_GPIO (3)
#define LWGPIO_MUX_SDHCB20_GPIO (3)
#define LWGPIO_MUX_SDHCB21_GPIO (3)
#define LWGPIO_MUX_SDHCB22_GPIO (3)
#define LWGPIO_MUX_SDHCB23_GPIO (3)
                                 
#define LWGPIO_MUX_IEEEA8_GPIO  (3)
#define LWGPIO_MUX_IEEEA11_GPIO (3)
#define LWGPIO_MUX_IEEEA12_GPIO (3)
#define LWGPIO_MUX_IEEEA13_GPIO (3)
#define LWGPIO_MUX_IEEEA14_GPIO (3)
#define LWGPIO_MUX_IEEEB1_GPIO  (3)
#define LWGPIO_MUX_IEEEB2_GPIO  (3)
#define LWGPIO_MUX_IEEEB3_GPIO  (3)
#define LWGPIO_MUX_IEEEB4_GPIO  (3)
#define LWGPIO_MUX_IEEEB5_GPIO  (3)
#define LWGPIO_MUX_IEEEB6_GPIO  (3)

#define LWGPIO_MUX_GTM7_GPIO  (3)
#define LWGPIO_MUX_GTM9_GPIO  (3)
#define LWGPIO_MUX_GTM10_GPIO (3)
#define LWGPIO_MUX_GTM15_GPIO (3)

#define LWGPIO_MUX_ETSEC0_GPIO  (3)



#endif
